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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_pciw_fifo_control.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5576d 19h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7611d 15h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7611d 15h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7617d 11h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7627d 19h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7752d 14h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7810d 11h /pci/tags/rel_6/rtl/verilog/pci_pciw_fifo_control.v

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