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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5583d 18h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7618d 13h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7624d 10h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7817d 10h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7918d 23h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
67 Changed BIST signals for RAMs. tadejm 7919d 04h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7925d 16h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
62 Added BIST signals for RAMs. mihad 7928d 09h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
58 Removed all logic from asynchronous reset network mihad 7941d 11h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
33 Added some testcases, removed un-needed fifo signals mihad 8145d 15h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
26 Modified testbench and fixed some bugs mihad 8159d 10h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8177d 11h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8296d 18h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v
2 New project directory structure mihad 8299d 11h /pci/tags/rel_6/rtl/verilog/pci_target_unit.v

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