URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5576d 20h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7611d 15h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7622d 10h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
86	Entered the option to disable no response counter in wb master.	mihad	7764d 13h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
79	Updated.	mihad	7810d 11h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
78	Old files with wrong names removed.	mihad	7810d 12h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
73	Bug fixes, testcases added.	mihad	7816d 12h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7929d 11h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7977d 17h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
33	Added some testcases, removed un-needed fifo signals	mihad	8138d 16h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v
18	* empty log message *	mihad	8170d 14h	/pci/tags/rel_6/rtl/verilog/pci_user_constants.v