URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [top.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5576d 20h	/pci/tags/rel_6/rtl/verilog/top.v
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7611d 15h	/pci/tags/rel_6/rtl/verilog/top.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7622d 10h	/pci/tags/rel_6/rtl/verilog/top.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7810d 11h	/pci/tags/rel_6/rtl/verilog/top.v
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7912d 01h	/pci/tags/rel_6/rtl/verilog/top.v
67	Changed BIST signals for RAMs.	tadejm	7912d 05h	/pci/tags/rel_6/rtl/verilog/top.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7918d 18h	/pci/tags/rel_6/rtl/verilog/top.v
62	Added BIST signals for RAMs.	mihad	7921d 11h	/pci/tags/rel_6/rtl/verilog/top.v
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8122d 21h	/pci/tags/rel_6/rtl/verilog/top.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8170d 13h	/pci/tags/rel_6/rtl/verilog/top.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8289d 20h	/pci/tags/rel_6/rtl/verilog/top.v
2	New project directory structure	mihad	8292d 13h	/pci/tags/rel_6/rtl/verilog/top.v