URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [bus_commands.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5582d 07h	/pci/tags/rel_7/rtl/verilog/bus_commands.v
114	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7616d 21h	/pci/tags/rel_7/rtl/verilog/bus_commands.v
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7974d 02h	/pci/tags/rel_7/rtl/verilog/bus_commands.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 00h	/pci/tags/rel_7/rtl/verilog/bus_commands.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8295d 07h	/pci/tags/rel_7/rtl/verilog/bus_commands.v
2	New project directory structure	mihad	8298d 00h	/pci/tags/rel_7/rtl/verilog/bus_commands.v