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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_bridge32.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5582d 07h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7616d 21h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7622d 23h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7627d 21h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7815d 23h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
69 Changed BIST signal names etc.. mihad 7914d 02h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7917d 12h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
67 Changed BIST signals for RAMs. tadejm 7917d 17h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7924d 05h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
62 Added BIST signals for RAMs. mihad 7926d 22h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8176d 00h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8295d 07h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v
2 New project directory structure mihad 8298d 00h /pci/tags/rel_7/rtl/verilog/pci_bridge32.v

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