URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [bench/] [verilog/] [pci_behaviorial_target.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5621d 03h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
121	This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'.		7648d 14h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7666d 17h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8022d 00h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8167d 04h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
26	Modified testbench and fixed some bugs	mihad	8196d 19h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v
19	* empty log message *	mihad	8214d 20h	/pci/tags/rel_WB_B3/bench/verilog/pci_behaviorial_target.v