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[/] [pci/] [tags/] [rel_WB_B3/] [bench/] [verilog/] [pci_testbench_defines.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5621d 03h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7648d 15h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7666d 18h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7672d 03h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
92 Update! mihad 7719d 09h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
73 Bug fixes, testcases added. mihad 7860d 19h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
69 Changed BIST signal names etc.. mihad 7952d 23h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
66 Changed empty status generation in pciw_fifo_control.v mihad 7959d 23h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7963d 01h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8012d 19h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8022d 01h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
26 Modified testbench and fixed some bugs mihad 8196d 19h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v
15 Initial testbench import. Still under development mihad 8214d 22h /pci/tags/rel_WB_B3/bench/verilog/pci_testbench_defines.v

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