URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [bench/] [verilog/] [pci_regression_constants.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5844d 05h	/pci/trunk/bench/verilog/pci_regression_constants.v
148	Changed minimum pci image size to 256 bytes because of some PC system problems with size of IO images.	mihad	7507d 22h	/pci/trunk/bench/verilog/pci_regression_constants.v
143	Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.	mihad	7551d 01h	/pci/trunk/bench/verilog/pci_regression_constants.v
140	Update! SPOCI Implemented!	mihad	7716d 02h	/pci/trunk/bench/verilog/pci_regression_constants.v
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7752d 02h	/pci/trunk/bench/verilog/pci_regression_constants.v
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7895d 05h	/pci/trunk/bench/verilog/pci_regression_constants.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8245d 03h	/pci/trunk/bench/verilog/pci_regression_constants.v
26	Modified testbench and fixed some bugs	mihad	8419d 21h	/pci/trunk/bench/verilog/pci_regression_constants.v
15	Initial testbench import. Still under development	mihad	8438d 00h	/pci/trunk/bench/verilog/pci_regression_constants.v