URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [trunk/] [bench/] [verilog/] [system.v] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5844d 08h	/pci/trunk/bench/verilog/system.v
152	Some regression tests were failing during completion expired testing.	mihad	7280d 02h	/pci/trunk/bench/verilog/system.v
151	Top now sends x's to inputs when output is enabled.	mihad	7473d 03h	/pci/trunk/bench/verilog/system.v
148	Changed minimum pci image size to 256 bytes because of some PC system problems with size of IO images.	mihad	7508d 01h	/pci/trunk/bench/verilog/system.v
143	Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.	mihad	7551d 04h	/pci/trunk/bench/verilog/system.v
142	Single PCI Master write fix.	mihad	7661d 00h	/pci/trunk/bench/verilog/system.v
140	Update! SPOCI Implemented!	mihad	7716d 05h	/pci/trunk/bench/verilog/system.v
138	added test_initial_all_conf_values mbist_ctrl_i replaced by mbist_en_i	fr2201	7732d 23h	/pci/trunk/bench/verilog/system.v
137	def_wb_imagex_addr_map defined correctly	fr2201	7743d 07h	/pci/trunk/bench/verilog/system.v
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7752d 06h	/pci/trunk/bench/verilog/system.v
122	mbist signals updated according to newest convention	markom	7815d 08h	/pci/trunk/bench/verilog/system.v
119	Added support for WB B3. Some testcases were updated.	tadejm	7871d 20h	/pci/trunk/bench/verilog/system.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7889d 23h	/pci/trunk/bench/verilog/system.v
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7895d 08h	/pci/trunk/bench/verilog/system.v
92	Update!	mihad	7942d 14h	/pci/trunk/bench/verilog/system.v
87	Updated acording to RTL changes.	mihad	8032d 01h	/pci/trunk/bench/verilog/system.v
81	Updated synchronization in top level fifo modules.	mihad	8074d 19h	/pci/trunk/bench/verilog/system.v
73	Bug fixes, testcases added.	mihad	8084d 01h	/pci/trunk/bench/verilog/system.v
69	Changed BIST signal names etc..	mihad	8176d 04h	/pci/trunk/bench/verilog/system.v
64	The testcase I just added in previous revision repaired	mihad	8186d 05h	/pci/trunk/bench/verilog/system.v

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[/] [pci/] [trunk/] [bench/] [verilog/] [system.v] - Rev 154

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