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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_bridge32.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5685d 09h /pci/trunk/rtl/verilog/pci_bridge32.v
150 The control inputs from PCI are now muxed with control outputs
using output enable state for given signal.		 mihad 7314d 03h /pci/trunk/rtl/verilog/pci_bridge32.v
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7349d 02h /pci/trunk/rtl/verilog/pci_bridge32.v
140 Update! SPOCI Implemented! mihad 7557d 05h /pci/trunk/rtl/verilog/pci_bridge32.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7593d 06h /pci/trunk/rtl/verilog/pci_bridge32.v
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7602d 05h /pci/trunk/rtl/verilog/pci_bridge32.v
128 Some warning cleanup. simons 7603d 08h /pci/trunk/rtl/verilog/pci_bridge32.v
122 mbist signals updated according to newest convention markom 7656d 08h /pci/trunk/rtl/verilog/pci_bridge32.v
115 Added signals for WB Master B3. tadejm 7712d 20h /pci/trunk/rtl/verilog/pci_bridge32.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7726d 01h /pci/trunk/rtl/verilog/pci_bridge32.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7730d 23h /pci/trunk/rtl/verilog/pci_bridge32.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7919d 00h /pci/trunk/rtl/verilog/pci_bridge32.v
69 Changed BIST signal names etc.. mihad 8017d 04h /pci/trunk/rtl/verilog/pci_bridge32.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8020d 14h /pci/trunk/rtl/verilog/pci_bridge32.v
67 Changed BIST signals for RAMs. tadejm 8020d 18h /pci/trunk/rtl/verilog/pci_bridge32.v
63 Added additional testcase and changed rst name in BIST to trst mihad 8027d 07h /pci/trunk/rtl/verilog/pci_bridge32.v
62 Added BIST signals for RAMs. mihad 8030d 00h /pci/trunk/rtl/verilog/pci_bridge32.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8279d 02h /pci/trunk/rtl/verilog/pci_bridge32.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8398d 09h /pci/trunk/rtl/verilog/pci_bridge32.v
2 New project directory structure mihad 8401d 02h /pci/trunk/rtl/verilog/pci_bridge32.v

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