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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_conf_space.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5685d 09h /pci/trunk/rtl/verilog/pci_conf_space.v
149 Removed some unused signals. mihad 7349d 01h /pci/trunk/rtl/verilog/pci_conf_space.v
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7349d 02h /pci/trunk/rtl/verilog/pci_conf_space.v
143 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.		 mihad 7392d 04h /pci/trunk/rtl/verilog/pci_conf_space.v
140 Update! SPOCI Implemented! mihad 7557d 05h /pci/trunk/rtl/verilog/pci_conf_space.v
137 def_wb_imagex_addr_map defined correctly fr2201 7584d 07h /pci/trunk/rtl/verilog/pci_conf_space.v
136 Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) fr2201 7584d 08h /pci/trunk/rtl/verilog/pci_conf_space.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7593d 06h /pci/trunk/rtl/verilog/pci_conf_space.v
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7720d 04h /pci/trunk/rtl/verilog/pci_conf_space.v
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7861d 04h /pci/trunk/rtl/verilog/pci_conf_space.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7919d 00h /pci/trunk/rtl/verilog/pci_conf_space.v

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