URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_master32_sm_if.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5685d 15h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
142	Single PCI Master write fix.	mihad	7502d 06h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7593d 12h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
94	Changed one critical PCI bus signal logic.	mihad	7783d 13h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7919d 06h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8279d 08h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8398d 15h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v
2	New project directory structure	mihad	8401d 07h	/pci/trunk/rtl/verilog/pci_master32_sm_if.v