URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_parity_check.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5717d 20h	/pci/trunk/rtl/verilog/pci_parity_check.v
83	Cleaned up the code. No functional changes.	mihad	7934d 10h	/pci/trunk/rtl/verilog/pci_parity_check.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7951d 11h	/pci/trunk/rtl/verilog/pci_parity_check.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8118d 17h	/pci/trunk/rtl/verilog/pci_parity_check.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8311d 13h	/pci/trunk/rtl/verilog/pci_parity_check.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8430d 20h	/pci/trunk/rtl/verilog/pci_parity_check.v
2	New project directory structure	mihad	8433d 13h	/pci/trunk/rtl/verilog/pci_parity_check.v