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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_target32_sm.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5717d 20h /pci/trunk/rtl/verilog/pci_target32_sm.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7625d 17h /pci/trunk/rtl/verilog/pci_target32_sm.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7758d 12h /pci/trunk/rtl/verilog/pci_target32_sm.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7951d 11h /pci/trunk/rtl/verilog/pci_target32_sm.v
73 Bug fixes, testcases added. mihad 7957d 12h /pci/trunk/rtl/verilog/pci_target32_sm.v
56 Number of state bits define was removed mihad 8076d 09h /pci/trunk/rtl/verilog/pci_target32_sm.v
55 Changed state machine encoding to true one-hot mihad 8076d 10h /pci/trunk/rtl/verilog/pci_target32_sm.v
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8109d 19h /pci/trunk/rtl/verilog/pci_target32_sm.v
26 Modified testbench and fixed some bugs mihad 8293d 12h /pci/trunk/rtl/verilog/pci_target32_sm.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8311d 13h /pci/trunk/rtl/verilog/pci_target32_sm.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8430d 20h /pci/trunk/rtl/verilog/pci_target32_sm.v
2 New project directory structure mihad 8433d 13h /pci/trunk/rtl/verilog/pci_target32_sm.v

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