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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5685d 14h /pci/trunk/rtl/verilog/pci_user_constants.v
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7349d 07h /pci/trunk/rtl/verilog/pci_user_constants.v
143 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.		 mihad 7392d 10h /pci/trunk/rtl/verilog/pci_user_constants.v
140 Update! SPOCI Implemented! mihad 7557d 11h /pci/trunk/rtl/verilog/pci_user_constants.v
137 def_wb_imagex_addr_map defined correctly fr2201 7584d 13h /pci/trunk/rtl/verilog/pci_user_constants.v
136 Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) fr2201 7584d 14h /pci/trunk/rtl/verilog/pci_user_constants.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7593d 12h /pci/trunk/rtl/verilog/pci_user_constants.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7731d 05h /pci/trunk/rtl/verilog/pci_user_constants.v
86 Entered the option to disable no response counter in wb master. mihad 7873d 07h /pci/trunk/rtl/verilog/pci_user_constants.v
79 Updated. mihad 7919d 06h /pci/trunk/rtl/verilog/pci_user_constants.v
78 Old files with wrong names removed. mihad 7919d 06h /pci/trunk/rtl/verilog/pci_user_constants.v
73 Bug fixes, testcases added. mihad 7925d 07h /pci/trunk/rtl/verilog/pci_user_constants.v
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8038d 05h /pci/trunk/rtl/verilog/pci_user_constants.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8086d 12h /pci/trunk/rtl/verilog/pci_user_constants.v
33 Added some testcases, removed un-needed fifo signals mihad 8247d 11h /pci/trunk/rtl/verilog/pci_user_constants.v
18 *** empty log message *** mihad 8279d 08h /pci/trunk/rtl/verilog/pci_user_constants.v

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