URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wb_master.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5685d 15h	/pci/trunk/rtl/verilog/pci_wb_master.v
140	Update! SPOCI Implemented!	mihad	7557d 11h	/pci/trunk/rtl/verilog/pci_wb_master.v
124	Added missing signals to 2 sensitivity lists. Everything works the same as before.	tadejm	7649d 13h	/pci/trunk/rtl/verilog/pci_wb_master.v
117	WB Master is now WISHBONE B3 compatible.	tadejm	7713d 02h	/pci/trunk/rtl/verilog/pci_wb_master.v
86	Entered the option to disable no response counter in wb master.	mihad	7873d 07h	/pci/trunk/rtl/verilog/pci_wb_master.v
81	Updated synchronization in top level fifo modules.	mihad	7916d 01h	/pci/trunk/rtl/verilog/pci_wb_master.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7919d 06h	/pci/trunk/rtl/verilog/pci_wb_master.v