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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wbs_wbb3_2_wbb2.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5685d 09h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
147 Removed unsinthesizable !== comparation. mihad 7352d 08h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
140 Update! SPOCI Implemented! mihad 7557d 05h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7593d 06h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7611d 01h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7722d 03h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v

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