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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wbs_wbb3_2_wbb2.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5844d 05h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
147 Removed unsinthesizable !== comparation. mihad 7511d 05h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
140 Update! SPOCI Implemented! mihad 7716d 02h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7752d 03h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7769d 21h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7881d 00h /pci/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v

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