URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wbw_wbr_fifos.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5685d 15h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
153	Write burst performance patch applied. Not tested. Everything should be backwards compatible, since functional code is ifdefed.	mihad	6665d 10h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7593d 12h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
122	mbist signals updated according to newest convention	markom	7656d 14h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7720d 10h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7861d 10h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
81	Updated synchronization in top level fifo modules.	mihad	7916d 01h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7919d 06h	/pci/trunk/rtl/verilog/pci_wbw_wbr_fifos.v