OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Rev 154

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5844d 10h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7508d 03h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
140 Update! SPOCI Implemented! mihad 7716d 07h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7752d 07h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
118 Some minor changes due to changes in core. tadejm 7871d 22h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7890d 01h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7895d 10h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
92 Update! mihad 7942d 16h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
81 Updated synchronization in top level fifo modules. mihad 8074d 21h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
73 Bug fixes, testcases added. mihad 8084d 03h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
63 Added additional testcase and changed rst name in BIST to trst mihad 8186d 09h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8197d 01h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8245d 08h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
26 Modified testbench and fixed some bugs mihad 8420d 02h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
17 *** empty log message *** mihad 8438d 05h /pci/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.