URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Rev 10

Rev	Log message	Author	Age	Path
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5665d 03h	/pit/trunk/rtl/verilog/pit_wb_bus.v
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5670d 21h	/pit/trunk/rtl/verilog/pit_wb_bus.v
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5713d 00h	/pit/trunk/rtl/verilog/pit_wb_bus.v