URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Rev 15

Rev	Log message	Author	Age	Path
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5609d 11h	/pit/trunk/rtl/verilog/pit_wb_bus.v
12	Fixed for single cycle reads	rehayes	5640d 10h	/pit/trunk/rtl/verilog/pit_wb_bus.v
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5641d 13h	/pit/trunk/rtl/verilog/pit_wb_bus.v
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5647d 07h	/pit/trunk/rtl/verilog/pit_wb_bus.v
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5689d 10h	/pit/trunk/rtl/verilog/pit_wb_bus.v