URL https://opencores.org/ocsvn/pit/pit/trunk

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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Rev 17

Rev	Log message	Author	Age	Path
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5377d 19h	/pit/trunk/rtl/verilog/pit_wb_bus.v
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5585d 21h	/pit/trunk/rtl/verilog/pit_wb_bus.v
12	Fixed for single cycle reads	rehayes	5616d 19h	/pit/trunk/rtl/verilog/pit_wb_bus.v
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5617d 22h	/pit/trunk/rtl/verilog/pit_wb_bus.v
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5623d 16h	/pit/trunk/rtl/verilog/pit_wb_bus.v
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5665d 19h	/pit/trunk/rtl/verilog/pit_wb_bus.v