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[/] [plasma/] [tags/] [V2_1/] [vhdl/] [mem_ctrl.vhd] - Rev 420

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Rev Log message Author Age Path
352 linus 5618d 12h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
350 root 5647d 08h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
127 This commit was manufactured by cvs2svn to create tag 'V2_1'. 7383d 19h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7564d 20h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
95 register mem_write and mem_byte_sel for speed calculations rhoads 8087d 23h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
89 Use address_reg instead of address_data to break timing slow down rhoads 8089d 17h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
72 accurate_timing, cleanup, pipeline rhoads 8097d 18h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
56 Altera, added byte_sel_reg for tigher timing and avoid possible glitches rhoads 8106d 00h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
49 Fix pause while writting rhoads 8116d 19h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
47 Altera rhoads 8123d 20h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
43 Renamed M-lite to Plasma rhoads 8203d 20h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8236d 01h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
8 Preparing to use dual-port memory for registers. rhoads 8272d 19h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8278d 02h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
6 JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts. rhoads 8282d 00h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd
2 MIPS-lite CPU core rhoads 8501d 01h /plasma/tags/V2_1/vhdl/mem_ctrl.vhd

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