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[/] [plasma/] [tags/] [V3_0/] [vhdl/] [reg_bank.vhd] - Rev 368

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352 linus 5619d 14h /plasma/tags/V3_0/vhdl/reg_bank.vhd
350 root 5648d 09h /plasma/tags/V3_0/vhdl/reg_bank.vhd
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6748d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6748d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7228d 20h /plasma/tags/V3_0/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7366d 07h /plasma/tags/V3_0/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7451d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7565d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7839d 18h /plasma/tags/V3_0/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8090d 18h /plasma/tags/V3_0/vhdl/reg_bank.vhd
74 pause in rhoads 8098d 20h /plasma/tags/V3_0/vhdl/reg_bank.vhd
55 Altera rhoads 8107d 01h /plasma/tags/V3_0/vhdl/reg_bank.vhd
48 Altera rhoads 8117d 20h /plasma/tags/V3_0/vhdl/reg_bank.vhd
47 Altera rhoads 8124d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8204d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8237d 02h /plasma/tags/V3_0/vhdl/reg_bank.vhd
24 Disable interrupts upon reset. rhoads 8261d 20h /plasma/tags/V3_0/vhdl/reg_bank.vhd
12 Better support for dual-port memories, removed old method rhoads 8267d 20h /plasma/tags/V3_0/vhdl/reg_bank.vhd
9 Support for generic_tpram dual-port RAM rhoads 8272d 23h /plasma/tags/V3_0/vhdl/reg_bank.vhd
8 Preparing to use dual-port memory for registers. rhoads 8273d 21h /plasma/tags/V3_0/vhdl/reg_bank.vhd

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