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[/] [plasma/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Rev 374

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Rev Log message Author Age Path
352 linus 5689d 11h /plasma/trunk/vhdl/mem_ctrl.vhd
350 root 5718d 06h /plasma/trunk/vhdl/mem_ctrl.vhd
264 Latch address and byte_we in mem_ctrl.vhd rhoads 6169d 05h /plasma/trunk/vhdl/mem_ctrl.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6818d 19h /plasma/trunk/vhdl/mem_ctrl.vhd
129 Added reset_in to sensitivity list rhoads 7317d 17h /plasma/trunk/vhdl/mem_ctrl.vhd
128 Reset all registers, constants now upper case. rhoads 7436d 05h /plasma/trunk/vhdl/mem_ctrl.vhd
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7635d 19h /plasma/trunk/vhdl/mem_ctrl.vhd
95 register mem_write and mem_byte_sel for speed calculations rhoads 8158d 22h /plasma/trunk/vhdl/mem_ctrl.vhd
89 Use address_reg instead of address_data to break timing slow down rhoads 8160d 16h /plasma/trunk/vhdl/mem_ctrl.vhd
72 accurate_timing, cleanup, pipeline rhoads 8168d 17h /plasma/trunk/vhdl/mem_ctrl.vhd
56 Altera, added byte_sel_reg for tigher timing and avoid possible glitches rhoads 8176d 22h /plasma/trunk/vhdl/mem_ctrl.vhd
49 Fix pause while writting rhoads 8187d 18h /plasma/trunk/vhdl/mem_ctrl.vhd
47 Altera rhoads 8194d 18h /plasma/trunk/vhdl/mem_ctrl.vhd
43 Renamed M-lite to Plasma rhoads 8274d 19h /plasma/trunk/vhdl/mem_ctrl.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8307d 00h /plasma/trunk/vhdl/mem_ctrl.vhd
8 Preparing to use dual-port memory for registers. rhoads 8343d 18h /plasma/trunk/vhdl/mem_ctrl.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8349d 01h /plasma/trunk/vhdl/mem_ctrl.vhd
6 JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts. rhoads 8352d 23h /plasma/trunk/vhdl/mem_ctrl.vhd
2 MIPS-lite CPU core rhoads 8571d 23h /plasma/trunk/vhdl/mem_ctrl.vhd

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