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[/] [plasma/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 404

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Rev	Log message	Author	Age	Path
352		linus	5726d 05h	/plasma/trunk/vhdl/mlite_cpu.vhd
350		root	5755d 00h	/plasma/trunk/vhdl/mlite_cpu.vhd
280	Fix comment	rhoads	6179d 13h	/plasma/trunk/vhdl/mlite_cpu.vhd
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6205d 22h	/plasma/trunk/vhdl/mlite_cpu.vhd
203	Fixed stages comment	rhoads	6444d 23h	/plasma/trunk/vhdl/mlite_cpu.vhd
202	Defined outputing PC as stage #0	rhoads	6445d 00h	/plasma/trunk/vhdl/mlite_cpu.vhd
194	Implemented BREAK and SYSCALL opcodes	rhoads	6509d 20h	/plasma/trunk/vhdl/mlite_cpu.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6855d 13h	/plasma/trunk/vhdl/mlite_cpu.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7335d 11h	/plasma/trunk/vhdl/mlite_cpu.vhd
128	Reset all registers, constants now upper case.	rhoads	7472d 22h	/plasma/trunk/vhdl/mlite_cpu.vhd
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7491d 12h	/plasma/trunk/vhdl/mlite_cpu.vhd
120	Make generics "GENERIC"	rhoads	7634d 01h	/plasma/trunk/vhdl/mlite_cpu.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7672d 12h	/plasma/trunk/vhdl/mlite_cpu.vhd
96	Simplify take_branch	rhoads	8195d 16h	/plasma/trunk/vhdl/mlite_cpu.vhd
83	Updated comments, accurate_timing on by default	rhoads	8197d 10h	/plasma/trunk/vhdl/mlite_cpu.vhd
73	pipeline, better reset	rhoads	8205d 11h	/plasma/trunk/vhdl/mlite_cpu.vhd
60	reset control	rhoads	8213d 16h	/plasma/trunk/vhdl/mlite_cpu.vhd
47	Altera	rhoads	8231d 12h	/plasma/trunk/vhdl/mlite_cpu.vhd
43	Renamed M-lite to Plasma	rhoads	8311d 12h	/plasma/trunk/vhdl/mlite_cpu.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8343d 18h	/plasma/trunk/vhdl/mlite_cpu.vhd

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[/] [plasma/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 404

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