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[/] [plasma/] [trunk/] [vhdl/] [mlite_pack.vhd] - Rev 395

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Rev Log message Author Age Path
383 Permit up to 64KB internal RAM and updated cache code. rhoads 5201d 00h /plasma/trunk/vhdl/mlite_pack.vhd
352 linus 5703d 14h /plasma/trunk/vhdl/mlite_pack.vhd
350 root 5732d 10h /plasma/trunk/vhdl/mlite_pack.vhd
346 Support optional 4KB cache rhoads 5800d 05h /plasma/trunk/vhdl/mlite_pack.vhd
332 Updated Altera lpm_ram_dp rhoads 5860d 23h /plasma/trunk/vhdl/mlite_pack.vhd
285 Added eth_dma rhoads 6140d 00h /plasma/trunk/vhdl/mlite_pack.vhd
264 Latch address and byte_we in mem_ctrl.vhd rhoads 6183d 08h /plasma/trunk/vhdl/mlite_pack.vhd
202 Defined outputing PC as stage #0 rhoads 6422d 09h /plasma/trunk/vhdl/mlite_pack.vhd
194 Implemented BREAK and SYSCALL opcodes rhoads 6487d 05h /plasma/trunk/vhdl/mlite_pack.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6832d 22h /plasma/trunk/vhdl/mlite_pack.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7312d 21h /plasma/trunk/vhdl/mlite_pack.vhd
128 Reset all registers, constants now upper case. rhoads 7450d 08h /plasma/trunk/vhdl/mlite_pack.vhd
125 Fixed pc_source_type comment. rhoads 7468d 21h /plasma/trunk/vhdl/mlite_pack.vhd
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7649d 22h /plasma/trunk/vhdl/mlite_pack.vhd
96 Simplify take_branch rhoads 8173d 01h /plasma/trunk/vhdl/mlite_pack.vhd
91 Removed unused alu_function_type entries rhoads 8174d 19h /plasma/trunk/vhdl/mlite_pack.vhd
70 pipeline rhoads 8182d 20h /plasma/trunk/vhdl/mlite_pack.vhd
62 updated LPM functions; mem_none->mem_fetch rhoads 8191d 01h /plasma/trunk/vhdl/mlite_pack.vhd
50 Update prototypes rhoads 8201d 21h /plasma/trunk/vhdl/mlite_pack.vhd
47 Altera rhoads 8208d 22h /plasma/trunk/vhdl/mlite_pack.vhd

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