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[/] [plasma/] [trunk/] [vhdl/] [mult.vhd] - Rev 393

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Rev Log message Author Age Path
391 Better fix for 0x8000000 * negative number rhoads 5176d 11h /plasma/trunk/vhdl/mult.vhd
390 Handle special case of signed mult of 0x80000000 and a negative number rhoads 5179d 10h /plasma/trunk/vhdl/mult.vhd
352 linus 5689d 02h /plasma/trunk/vhdl/mult.vhd
350 root 5717d 21h /plasma/trunk/vhdl/mult.vhd
345 Commented out optional mult speedup rhoads 5789d 13h /plasma/trunk/vhdl/mult.vhd
196 Explained how to remove mult.vhd and use SW multiplication and division. rhoads 6455d 13h /plasma/trunk/vhdl/mult.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6818d 09h /plasma/trunk/vhdl/mult.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7298d 08h /plasma/trunk/vhdl/mult.vhd
128 Reset all registers, constants now upper case. rhoads 7435d 19h /plasma/trunk/vhdl/mult.vhd
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7596d 22h /plasma/trunk/vhdl/mult.vhd
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7635d 09h /plasma/trunk/vhdl/mult.vhd
99 correct upper 32-bits for mult(-1,-1) rhoads 8055d 07h /plasma/trunk/vhdl/mult.vhd
97 added documentation rhoads 8124d 11h /plasma/trunk/vhdl/mult.vhd
90 Now multiplies two bits at a time rhoads 8160d 06h /plasma/trunk/vhdl/mult.vhd
47 Altera rhoads 8194d 09h /plasma/trunk/vhdl/mult.vhd
45 Fixed signed 64-bit multiply rhoads 8271d 22h /plasma/trunk/vhdl/mult.vhd
43 Renamed M-lite to Plasma rhoads 8274d 09h /plasma/trunk/vhdl/mult.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8306d 14h /plasma/trunk/vhdl/mult.vhd
23 Fixed div -x/y. rhoads 8331d 08h /plasma/trunk/vhdl/mult.vhd
18 Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0. rhoads 8333d 08h /plasma/trunk/vhdl/mult.vhd

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