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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 352

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Rev Log message Author Age Path
352 linus 5717d 10h /plasma/trunk/vhdl/reg_bank.vhd
350 root 5746d 05h /plasma/trunk/vhdl/reg_bank.vhd
344 Fixed compiler warning rhoads 5817d 21h /plasma/trunk/vhdl/reg_bank.vhd
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5874d 19h /plasma/trunk/vhdl/reg_bank.vhd
261 Removed commented out lines rhoads 6197d 03h /plasma/trunk/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6846d 17h /plasma/trunk/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7326d 16h /plasma/trunk/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7464d 03h /plasma/trunk/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7549d 17h /plasma/trunk/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7663d 17h /plasma/trunk/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7937d 14h /plasma/trunk/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8188d 14h /plasma/trunk/vhdl/reg_bank.vhd
74 pause in rhoads 8196d 16h /plasma/trunk/vhdl/reg_bank.vhd
55 Altera rhoads 8204d 21h /plasma/trunk/vhdl/reg_bank.vhd
48 Altera rhoads 8215d 16h /plasma/trunk/vhdl/reg_bank.vhd
47 Altera rhoads 8222d 17h /plasma/trunk/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8302d 17h /plasma/trunk/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8334d 22h /plasma/trunk/vhdl/reg_bank.vhd
24 Disable interrupts upon reset. rhoads 8359d 16h /plasma/trunk/vhdl/reg_bank.vhd
12 Better support for dual-port memories, removed old method rhoads 8365d 16h /plasma/trunk/vhdl/reg_bank.vhd

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