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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 378

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Rev Log message Author Age Path
376 Add write_enable to sensitivity list for Altera rhoads 5360d 00h /plasma/trunk/vhdl/reg_bank.vhd
365 Added UNISIM comment rhoads 5618d 14h /plasma/trunk/vhdl/reg_bank.vhd
352 linus 5719d 06h /plasma/trunk/vhdl/reg_bank.vhd
350 root 5748d 02h /plasma/trunk/vhdl/reg_bank.vhd
344 Fixed compiler warning rhoads 5819d 18h /plasma/trunk/vhdl/reg_bank.vhd
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5876d 16h /plasma/trunk/vhdl/reg_bank.vhd
261 Removed commented out lines rhoads 6199d 00h /plasma/trunk/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6848d 14h /plasma/trunk/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7328d 13h /plasma/trunk/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7466d 00h /plasma/trunk/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7551d 14h /plasma/trunk/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7665d 14h /plasma/trunk/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7939d 10h /plasma/trunk/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8190d 11h /plasma/trunk/vhdl/reg_bank.vhd
74 pause in rhoads 8198d 12h /plasma/trunk/vhdl/reg_bank.vhd
55 Altera rhoads 8206d 18h /plasma/trunk/vhdl/reg_bank.vhd
48 Altera rhoads 8217d 13h /plasma/trunk/vhdl/reg_bank.vhd
47 Altera rhoads 8224d 14h /plasma/trunk/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8304d 14h /plasma/trunk/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8336d 19h /plasma/trunk/vhdl/reg_bank.vhd

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