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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 395

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Rev Log message Author Age Path
376 Add write_enable to sensitivity list for Altera rhoads 5344d 08h /plasma/trunk/vhdl/reg_bank.vhd
365 Added UNISIM comment rhoads 5602d 22h /plasma/trunk/vhdl/reg_bank.vhd
352 linus 5703d 14h /plasma/trunk/vhdl/reg_bank.vhd
350 root 5732d 10h /plasma/trunk/vhdl/reg_bank.vhd
344 Fixed compiler warning rhoads 5804d 02h /plasma/trunk/vhdl/reg_bank.vhd
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5861d 00h /plasma/trunk/vhdl/reg_bank.vhd
261 Removed commented out lines rhoads 6183d 08h /plasma/trunk/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6832d 22h /plasma/trunk/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7312d 21h /plasma/trunk/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7450d 08h /plasma/trunk/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7535d 22h /plasma/trunk/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7649d 22h /plasma/trunk/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7923d 19h /plasma/trunk/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8174d 19h /plasma/trunk/vhdl/reg_bank.vhd
74 pause in rhoads 8182d 21h /plasma/trunk/vhdl/reg_bank.vhd
55 Altera rhoads 8191d 02h /plasma/trunk/vhdl/reg_bank.vhd
48 Altera rhoads 8201d 21h /plasma/trunk/vhdl/reg_bank.vhd
47 Altera rhoads 8208d 22h /plasma/trunk/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8288d 22h /plasma/trunk/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8321d 03h /plasma/trunk/vhdl/reg_bank.vhd

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