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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 408

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Rev Log message Author Age Path
397 Added RAM32X1D option rhoads 5053d 22h /plasma/trunk/vhdl/reg_bank.vhd
376 Add write_enable to sensitivity list for Altera rhoads 5359d 11h /plasma/trunk/vhdl/reg_bank.vhd
365 Added UNISIM comment rhoads 5618d 02h /plasma/trunk/vhdl/reg_bank.vhd
352 linus 5718d 18h /plasma/trunk/vhdl/reg_bank.vhd
350 root 5747d 13h /plasma/trunk/vhdl/reg_bank.vhd
344 Fixed compiler warning rhoads 5819d 05h /plasma/trunk/vhdl/reg_bank.vhd
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5876d 03h /plasma/trunk/vhdl/reg_bank.vhd
261 Removed commented out lines rhoads 6198d 12h /plasma/trunk/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6848d 01h /plasma/trunk/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7328d 00h /plasma/trunk/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7465d 11h /plasma/trunk/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7551d 01h /plasma/trunk/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7665d 01h /plasma/trunk/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7938d 22h /plasma/trunk/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8189d 22h /plasma/trunk/vhdl/reg_bank.vhd
74 pause in rhoads 8198d 00h /plasma/trunk/vhdl/reg_bank.vhd
55 Altera rhoads 8206d 05h /plasma/trunk/vhdl/reg_bank.vhd
48 Altera rhoads 8217d 00h /plasma/trunk/vhdl/reg_bank.vhd
47 Altera rhoads 8224d 01h /plasma/trunk/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8304d 01h /plasma/trunk/vhdl/reg_bank.vhd

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