URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Rev 51

Rev	Log message	Author	Age	Path
45	Merge branch cache-playground (r23-r30 and r34-r44) into trunk This primarily adds the following features the the processor: - A direct-mapped instruction cache with configurable cache line width and number of cache lines. - Various bug fixes for bugs that appeared when the processor could run instructions at full speed but had to stall for data. - A "Hello World" test application.	skordal	3466d 04h	/potato/trunk/example/toplevel.vhd
21	Upgrade the example design to use a 60 MHz system clock	skordal	3483d 03h	/potato/trunk/example/toplevel.vhd
12	Update example design with correct bug-report URL and testbenches	skordal	3496d 10h	/potato/trunk/example/toplevel.vhd
7	Add test design for the Nexys 4 board from Digilent	skordal	3508d 07h	/potato/trunk/example/toplevel.vhd