URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Rev 62

Rev	Log message	Author	Age	Path
62	Add a couple of missing signals to a sensitivity list	skordal	3376d 09h	/potato/trunk/example/toplevel.vhd
61	Add 7-segment display controller to the Potato SoC	skordal	3377d 12h	/potato/trunk/example/toplevel.vhd
58	Merge branch new-privileged-isa (r48-r57) into trunk This adds support for the newly published supervisor extensions version 1.7. In addition, a processor datasheet has been added and the timer_clk signal has been properly connected in the example design and the SoC testbench.	skordal	3411d 09h	/potato/trunk/example/toplevel.vhd
45	Merge branch cache-playground (r23-r30 and r34-r44) into trunk This primarily adds the following features the the processor: - A direct-mapped instruction cache with configurable cache line width and number of cache lines. - Various bug fixes for bugs that appeared when the processor could run instructions at full speed but had to stall for data. - A "Hello World" test application.	skordal	3443d 04h	/potato/trunk/example/toplevel.vhd
21	Upgrade the example design to use a 60 MHz system clock	skordal	3460d 02h	/potato/trunk/example/toplevel.vhd
12	Update example design with correct bug-report URL and testbenches	skordal	3473d 09h	/potato/trunk/example/toplevel.vhd
7	Add test design for the Nexys 4 board from Digilent	skordal	3485d 06h	/potato/trunk/example/toplevel.vhd