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[/] [qspiflash/] [trunk/] [doc/] [src/] [spec.tex] - Rev 14

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14 Updates: little-big endian, various other fixes

1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none
2. Changed the internal flash representation to big endian. A little-big
endian conversion is now required when writing to the flash from a PC.
3. Simplified the address description via w_wb_addr and w_spif_addr, so that
the core is more flexible when changing sizes.
4. Removed the dependence upon the WB_CYC line ... as part of the WB
simplifications I've been doing.
5. Got XIP working for the EQSPI flash (I guess --- it's been a while since
I made those changes)
6. Adjusted (fixed) sim of read/writes to the volatile config register
(necessary for XIP)		 dgisselq 2761d 21h /qspiflash/trunk/doc/src/spec.tex
9 Minor changes to the baseline, FIRST RELEASE OF THE EQSPIFLASH controller!! dgisselq 3048d 12h /qspiflash/trunk/doc/src/spec.tex
6 Minor documentation (formatting) changes. dgisselq 3467d 15h /qspiflash/trunk/doc/src/spec.tex
5 Minor changes to the documentation. dgisselq 3474d 19h /qspiflash/trunk/doc/src/spec.tex
3 This quick update fixes some oopses associated with the original release.
Specifically, I made sure the license comments were available in all source
files, made sure all source files mentioned that they were a part of a Quad
SPI flash controller, rather than the Basys-3 development board project they
were originally a part of or the Spartan 3E project before that, I took out
the (undocumented) debug "scaffolding" that was still in the Verilog files,
and I added the C++ source for the bench test/simulator into the project.
Although the full bench test is not complete, it should be sufficient for
anyone who would wish to test this within Verilator.

These changes should not affect any of the functionality of the core.		 dgisselq 3486d 08h /qspiflash/trunk/doc/src/spec.tex
2 Initial submission. dgisselq 3486d 10h /qspiflash/trunk/doc/src/spec.tex

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