URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [rtl/] [eqspiflash.v] - Rev 14

Rev	Log message	Author	Age	Path
14	Updates: little-big endian, various other fixes 1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none 2. Changed the internal flash representation to big endian. A little-big endian conversion is now required when writing to the flash from a PC. 3. Simplified the address description via w_wb_addr and w_spif_addr, so that the core is more flexible when changing sizes. 4. Removed the dependence upon the WB_CYC line ... as part of the WB simplifications I've been doing. 5. Got XIP working for the EQSPI flash (I guess --- it's been a while since I made those changes) 6. Adjusted (fixed) sim of read/writes to the volatile config register (necessary for XIP)	dgisselq	2758d 03h	/qspiflash/trunk/rtl/eqspiflash.v
11	This code has been proven, and is currently working within an Arty platform.	dgisselq	3027d 18h	/qspiflash/trunk/rtl/eqspiflash.v
10	Switched to Quad Output mode by default.	dgisselq	3044d 15h	/qspiflash/trunk/rtl/eqspiflash.v
9	Minor changes to the baseline, FIRST RELEASE OF THE EQSPIFLASH controller!!	dgisselq	3044d 17h	/qspiflash/trunk/rtl/eqspiflash.v