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[/] [raytrac/] [branches/] [fp/] [dpc.vhd] - Rev 169

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Rev	Log message	Author	Age	Path
167	Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync	jguarin2002	4545d 06h	/raytrac/branches/fp/dpc.vhd
163	dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions.	jguarin2002	4547d 04h	/raytrac/branches/fp/dpc.vhd
161	Changes for the sake of the firsts simulation tracking results	jguarin2002	4548d 20h	/raytrac/branches/fp/dpc.vhd
160	Corrections derived from simulation debugging	jguarin2002	4553d 12h	/raytrac/branches/fp/dpc.vhd
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4555d 02h	/raytrac/branches/fp/dpc.vhd
153	last modifications for tb_compiler.py compliance	jguarin2002	4561d 18h	/raytrac/branches/fp/dpc.vhd
152	Test bench oriented modifications	jguarin2002	4565d 20h	/raytrac/branches/fp/dpc.vhd
151	Previous Work to generate test benching	jguarin2002	4624d 15h	/raytrac/branches/fp/dpc.vhd
150	First Beta of RayTrac for a total size of 3874 lcells. Great Result\!	jguarin2002	4638d 13h	/raytrac/branches/fp/dpc.vhd
149	Results Queue writing signals set on a single standard logic vector rather than in individual bits	jguarin2002	4638d 16h	/raytrac/branches/fp/dpc.vhd
148	Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B	jguarin2002	4638d 16h	/raytrac/branches/fp/dpc.vhd
147	Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified.	jguarin2002	4641d 04h	/raytrac/branches/fp/dpc.vhd
145	State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig	jguarin2002	4653d 12h	/raytrac/branches/fp/dpc.vhd
144	The commented part of DPC was erased, and no longer needed.	jguarin2002	4660d 16h	/raytrac/branches/fp/dpc.vhd
143	working on result queue sync decoding signals	jguarin2002	4665d 08h	/raytrac/branches/fp/dpc.vhd
142	Additions for the State Machine	jguarin2002	4670d 06h	/raytrac/branches/fp/dpc.vhd
140	Syncing: its awful work.....	jguarin2002	4737d 13h	/raytrac/branches/fp/dpc.vhd
139	Sync	jguarin2002	4749d 04h	/raytrac/branches/fp/dpc.vhd
138	enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes	jguarin2002	4753d 19h	/raytrac/branches/fp/dpc.vhd
136	gogogo	jguarin2002	4762d 06h	/raytrac/branches/fp/dpc.vhd

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[/] [raytrac/] [branches/] [fp/] [dpc.vhd] - Rev 169

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