OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp/] [fadd32.vhd] - Rev 189

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
170 Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder jguarin2002 4596d 07h /raytrac/branches/fp/fadd32.vhd
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4599d 08h /raytrac/branches/fp/fadd32.vhd
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4599d 17h /raytrac/branches/fp/fadd32.vhd
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4600d 18h /raytrac/branches/fp/fadd32.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4600d 20h /raytrac/branches/fp/fadd32.vhd
160 Corrections derived from simulation debugging jguarin2002 4607d 04h /raytrac/branches/fp/fadd32.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4608d 18h /raytrac/branches/fp/fadd32.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4609d 06h /raytrac/branches/fp/fadd32.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4612d 18h /raytrac/branches/fp/fadd32.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4615d 10h /raytrac/branches/fp/fadd32.vhd
152 Test bench oriented modifications jguarin2002 4619d 11h /raytrac/branches/fp/fadd32.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4692d 04h /raytrac/branches/fp/fadd32.vhd
139 Sync jguarin2002 4802d 19h /raytrac/branches/fp/fadd32.vhd
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4813d 11h /raytrac/branches/fp/fadd32.vhd
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4858d 23h /raytrac/branches/fp/fadd32.vhd
120 Beta 0 Adder LCELLS 373 jguarin2002 4864d 21h /raytrac/branches/fp/fadd32.vhd
119 382 LEs Adder, RTL viewer Check Ok jguarin2002 4865d 03h /raytrac/branches/fp/fadd32.vhd
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 4865d 10h /raytrac/branches/fp/fadd32.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.