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[/] [raytrac/] [branches/] [fp/] [fmul32.vhd] - Rev 157

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Rev Log message Author Age Path
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4753d 09h /raytrac/branches/fp/fmul32.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4756d 21h /raytrac/branches/fp/fmul32.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4759d 13h /raytrac/branches/fp/fmul32.vhd
152 Test bench oriented modifications jguarin2002 4763d 14h /raytrac/branches/fp/fmul32.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4836d 07h /raytrac/branches/fp/fmul32.vhd
139 Sync jguarin2002 4946d 22h /raytrac/branches/fp/fmul32.vhd
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4957d 14h /raytrac/branches/fp/fmul32.vhd
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 5003d 02h /raytrac/branches/fp/fmul32.vhd
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 5009d 13h /raytrac/branches/fp/fmul32.vhd
96 2 floating points operands multiplication done and optimized jguarin2002 5047d 12h /fmul32.vhd
94 Optimization on the functionality of the mantissa multiplier... the results are much more precise than last revision... jguarin2002 5049d 08h /fmul32.vhd
93 New Fpbranch Directory Distribution jguarin2002 5049d 18h /fmul32.vhd
89 floating point mult ready jguarin2002 5052d 14h /fmul32.vhd
86 For the sake of easyness, mmp is called now mul2 jguarin2002 5054d 15h /fmul32.vhd
82 FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd jguarin2002 5058d 02h /fmul32.vhd

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