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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Rev 181

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181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4703d 23h /raytrac/branches/fp/memblock.vhd
174 Comment tweaking... its the same RTL anyway jguarin2002 4740d 10h /raytrac/branches/fp/memblock.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4746d 14h /raytrac/branches/fp/memblock.vhd
160 Corrections derived from simulation debugging jguarin2002 4751d 07h /raytrac/branches/fp/memblock.vhd
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4752d 16h /raytrac/branches/fp/memblock.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4752d 21h /raytrac/branches/fp/memblock.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4753d 08h /raytrac/branches/fp/memblock.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4759d 13h /raytrac/branches/fp/memblock.vhd
152 Test bench oriented modifications jguarin2002 4763d 14h /raytrac/branches/fp/memblock.vhd
151 Previous Work to generate test benching jguarin2002 4822d 10h /raytrac/branches/fp/memblock.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4836d 07h /raytrac/branches/fp/memblock.vhd
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4838d 23h /raytrac/branches/fp/memblock.vhd
143 working on result queue sync decoding signals jguarin2002 4863d 02h /raytrac/branches/fp/memblock.vhd
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4935d 02h /raytrac/branches/fp/memblock.vhd
140 Syncing: its awful work..... jguarin2002 4935d 08h /raytrac/branches/fp/memblock.vhd
139 Sync jguarin2002 4946d 22h /raytrac/branches/fp/memblock.vhd
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4951d 13h /raytrac/branches/fp/memblock.vhd
136 gogogo jguarin2002 4960d 01h /raytrac/branches/fp/memblock.vhd
133 Added the instructions queue jguarin2002 4967d 13h /raytrac/branches/fp/memblock.vhd
131 Post RTL check on memblock jguarin2002 4971d 14h /raytrac/branches/fp/memblock.vhd

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