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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Rev 188

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Rev	Log message	Author	Age	Path
181	Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC	jguarin2002	4556d 05h	/raytrac/branches/fp/memblock.vhd
174	Comment tweaking... its the same RTL anyway	jguarin2002	4592d 16h	/raytrac/branches/fp/memblock.vhd
161	Changes for the sake of the firsts simulation tracking results	jguarin2002	4598d 20h	/raytrac/branches/fp/memblock.vhd
160	Corrections derived from simulation debugging	jguarin2002	4603d 13h	/raytrac/branches/fp/memblock.vhd
159	wrcycle\!\? No\! rwcycle....	jguarin2002	4604d 22h	/raytrac/branches/fp/memblock.vhd
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4605d 03h	/raytrac/branches/fp/memblock.vhd
157	For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim	jguarin2002	4605d 14h	/raytrac/branches/fp/memblock.vhd
153	last modifications for tb_compiler.py compliance	jguarin2002	4611d 19h	/raytrac/branches/fp/memblock.vhd
152	Test bench oriented modifications	jguarin2002	4615d 20h	/raytrac/branches/fp/memblock.vhd
151	Previous Work to generate test benching	jguarin2002	4674d 16h	/raytrac/branches/fp/memblock.vhd
150	First Beta of RayTrac for a total size of 3874 lcells. Great Result\!	jguarin2002	4688d 13h	/raytrac/branches/fp/memblock.vhd
147	Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified.	jguarin2002	4691d 04h	/raytrac/branches/fp/memblock.vhd
143	working on result queue sync decoding signals	jguarin2002	4715d 08h	/raytrac/branches/fp/memblock.vhd
141	Syncing: its awful work: input adresses decoded to include the instructions queue also....	jguarin2002	4787d 08h	/raytrac/branches/fp/memblock.vhd
140	Syncing: its awful work.....	jguarin2002	4787d 14h	/raytrac/branches/fp/memblock.vhd
139	Sync	jguarin2002	4799d 04h	/raytrac/branches/fp/memblock.vhd
138	enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes	jguarin2002	4803d 19h	/raytrac/branches/fp/memblock.vhd
136	gogogo	jguarin2002	4812d 07h	/raytrac/branches/fp/memblock.vhd
133	Added the instructions queue	jguarin2002	4819d 19h	/raytrac/branches/fp/memblock.vhd
131	Post RTL check on memblock	jguarin2002	4823d 20h	/raytrac/branches/fp/memblock.vhd

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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Rev 188

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