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[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [single/] [fadd32long.vhd] - Rev 244

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238 wide multiplicator added to avoid optimization jguarin2002 4475d 10h /raytrac/branches/fp_sgdma/arith/single/fadd32long.vhd
230 RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging jguarin2002 4481d 18h /fadd32long.vhd
229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4482d 18h /fadd32long.vhd
228 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4484d 11h /fadd32long.vhd
227 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4484d 14h /fadd32long.vhd
169 Long Stupid, version of a 32 bit floating point I3E754 Adder jguarin2002 4599d 04h /fadd32long.vhd
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4602d 05h /fadd32long.vhd
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4602d 14h /fadd32long.vhd
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4603d 15h /fadd32long.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4603d 17h /fadd32long.vhd
160 Corrections derived from simulation debugging jguarin2002 4610d 01h /fadd32long.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4611d 15h /fadd32long.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4612d 02h /fadd32long.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4615d 15h /fadd32long.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4618d 07h /fadd32long.vhd
152 Test bench oriented modifications jguarin2002 4622d 08h /fadd32long.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4695d 01h /fadd32long.vhd
139 Sync jguarin2002 4805d 16h /fadd32long.vhd
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4816d 08h /fadd32long.vhd
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4861d 20h /fadd32long.vhd

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