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[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [wide/] [fmul32.vhd] - Rev 246

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Rev	Log message	Author	Age	Path
241	fmul32 x 6 multipliers wide	jguarin2002	4457d 19h	/raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
240	last minute correction	jguarin2002	4457d 23h	/raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
239	wide multiplicator added to avoid optimization	jguarin2002	4458d 00h	/raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
238	wide multiplicator added to avoid optimization	jguarin2002	4458d 00h	/raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
219	RayTrac: Non tested and witouh TSE	jguarin2002	4476d 17h	/fmul32.vhd
196	raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues	jguarin2002	4518d 21h	/fmul32.vhd
160	Corrections derived from simulation debugging	jguarin2002	4592d 15h	/fmul32.vhd
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4594d 05h	/fmul32.vhd
157	For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim	jguarin2002	4594d 16h	/fmul32.vhd
155	Changes applied prior to testbenching using the script tb_compiler.py	jguarin2002	4598d 05h	/fmul32.vhd
153	last modifications for tb_compiler.py compliance	jguarin2002	4600d 21h	/fmul32.vhd
152	Test bench oriented modifications	jguarin2002	4604d 22h	/fmul32.vhd
150	First Beta of RayTrac for a total size of 3874 lcells. Great Result\!	jguarin2002	4677d 15h	/fmul32.vhd
139	Sync	jguarin2002	4788d 06h	/fmul32.vhd
137	Syncing with enables and eleminated all the register outputs since none block should carry on a register output	jguarin2002	4798d 22h	/fmul32.vhd
121	taking out std_logic_arith from sight.... no conversions allowed	jguarin2002	4844d 10h	/fmul32.vhd
118	fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32	jguarin2002	4850d 21h	/fmul32.vhd
96	2 floating points operands multiplication done and optimized	jguarin2002	4888d 19h	/fmul32.vhd
94	Optimization on the functionality of the mantissa multiplier... the results are much more precise than last revision...	jguarin2002	4890d 16h	/fmul32.vhd
93	New Fpbranch Directory Distribution	jguarin2002	4891d 02h	/fmul32.vhd

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Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [wide/] [fmul32.vhd] - Rev 246

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