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[/] [raytrac/] [branches/] [fp_sgdma/] [arithpack.vhd] - Rev 245

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229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4462d 15h /raytrac/branches/fp_sgdma/arithpack.vhd
219 RayTrac: Non tested and witouh TSE jguarin2002 4474d 01h /raytrac/branches/fp_sgdma/arithpack.vhd
213 Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) jguarin2002 4474d 20h /raytrac/branches/fp_sgdma/arithpack.vhd
203 Working towards a DMA oriented RayTRac jguarin2002 4486d 09h /raytrac/branches/fp_sgdma/arithpack.vhd
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4516d 04h /raytrac/branches/fp_sgdma/arithpack.vhd
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4540d 06h /arithpack.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4542d 15h /arithpack.vhd
173 Added a procedure to support vectorblock03 type variables rendering after testbench execution jguarin2002 4579d 02h /arithpack.vhd
168 Added a display function for vectorblock02 jguarin2002 4581d 16h /arithpack.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4583d 14h /arithpack.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4585d 06h /arithpack.vhd
160 Corrections derived from simulation debugging jguarin2002 4589d 22h /arithpack.vhd
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4591d 08h /arithpack.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4591d 12h /arithpack.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4592d 00h /arithpack.vhd
156 Test Bench Beta 0.1 jguarin2002 4592d 12h /arithpack.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4595d 12h /arithpack.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4598d 04h /arithpack.vhd
152 Test bench oriented modifications jguarin2002 4602d 05h /arithpack.vhd
151 Previous Work to generate test benching jguarin2002 4661d 01h /arithpack.vhd

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