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[/] [raytrac/] [branches/] [fp_sgdma/] [deprecated/] [fadd32.vhd] - Rev 246

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244 Changed the directory structure a little bit, there is now wide arith (which encapsulates in a single RTL 3 adders or 3 adders jguarin2002 4473d 16h /raytrac/branches/fp_sgdma/deprecated/fadd32.vhd
219 RayTrac: Non tested and witouh TSE jguarin2002 4493d 10h /fadd32.vhd
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4535d 13h /fadd32.vhd
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4559d 09h /fadd32.vhd
170 Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder jguarin2002 4598d 11h /fadd32.vhd
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4601d 11h /fadd32.vhd
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4601d 20h /fadd32.vhd
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4602d 21h /fadd32.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4602d 23h /fadd32.vhd
160 Corrections derived from simulation debugging jguarin2002 4609d 07h /fadd32.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4610d 21h /fadd32.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4611d 09h /fadd32.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4614d 21h /fadd32.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4617d 13h /fadd32.vhd
152 Test bench oriented modifications jguarin2002 4621d 15h /fadd32.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4694d 08h /fadd32.vhd
139 Sync jguarin2002 4804d 23h /fadd32.vhd
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4815d 15h /fadd32.vhd
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4861d 02h /fadd32.vhd
120 Beta 0 Adder LCELLS 373 jguarin2002 4867d 01h /fadd32.vhd

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