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[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac.vhd] - Rev 196

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196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4529d 19h /raytrac/branches/fp_sgdma/raytrac.vhd
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4555d 04h /raytrac.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4556d 05h /raytrac.vhd
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4580d 17h /raytrac.vhd
172 Results fifo writing signals added to the testbench jguarin2002 4592d 16h /raytrac.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4597d 05h /raytrac.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4598d 20h /raytrac.vhd
160 Corrections derived from simulation debugging jguarin2002 4603d 13h /raytrac.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4605d 03h /raytrac.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4605d 14h /raytrac.vhd
152 Test bench oriented modifications jguarin2002 4615d 20h /raytrac.vhd
151 Previous Work to generate test benching jguarin2002 4674d 16h /raytrac.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4688d 13h /raytrac.vhd

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