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[/] [raytrac/] [trunk/] [arithpack.vhd] - Rev 47

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47 Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation jguarin2002 5008d 23h /raytrac/trunk/arithpack.vhd
45 Magic is already written... now we shall set the testbench on fire\! jguarin2002 5010d 13h /raytrac/trunk/arithpack.vhd
44 All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... jguarin2002 5011d 14h /raytrac/trunk/arithpack.vhd
43 Nothing to say, just working on the Test Bench... jguarin2002 5011d 22h /raytrac/trunk/arithpack.vhd
42 no comment no tb yet: jguarin2002 5012d 16h /raytrac/trunk/arithpack.vhd
40 test bench changes..... jguarin2002 5015d 03h /raytrac/trunk/arithpack.vhd
32 carry_logic parameter added to uf entity jguarin2002 5025d 05h /raytrac/trunk/arithpack.vhd
27 Optimized code, using IEEE libraries and extra parameters to make a more legible code jguarin2002 5039d 12h /raytrac/trunk/arithpack.vhd
26 Corrections on opcoder jguarin2002 5039d 16h /raytrac/trunk/arithpack.vhd
25 Support to variable width and the possibility to choose between behavioral description and structural description jguarin2002 5039d 16h /raytrac/trunk/arithpack.vhd
24 Added a more simple mux to opcoder implementation. jguarin2002 5046d 09h /raytrac/trunk/arithpack.vhd
23 Doxygen documentation related changes..... jguarin2002 5046d 09h /raytrac/trunk/arithpack.vhd
22 Doxygen Documentation related changes. jguarin2002 5047d 01h /raytrac/trunk/arithpack.vhd
16 Commiting differences related to Doxygen documentation adding jguarin2002 5051d 14h /raytrac/trunk/arithpack.vhd
15 When selecting s0name, s1name, for a signal that belongs to a 2 stage pipe, the compiler would, based on the name, create just a single flipflop with Q feedbacking D, and that's no the case, so a lot of names has been changed, from s0signalname, s1signalname to stage0signalname, s1signalname and so on... jguarin2002 5054d 02h /raytrac/trunk/arithpack.vhd
14 Lots of typos fixed...... jguarin2002 5056d 02h /raytrac/trunk/arithpack.vhd
13 syntax typo fixed... jguarin2002 5056d 04h /raytrac/trunk/arithpack.vhd
12 syntax typo fixed... jguarin2002 5056d 04h /raytrac/trunk/arithpack.vhd
10 arithpack component declaration changed to make a more 'understandable' design, perhaps wont be that legible but at this stage, at least to me it is jguarin2002 5061d 19h /raytrac/trunk/arithpack.vhd
9 dumped fastmux, did not need it at all (by now), therefore arithpack.vhd was modified, by deleting the fastmux component declaration jguarin2002 5061d 22h /raytrac/trunk/arithpack.vhd

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