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[/] [raytrac/] [trunk/] [fpbranch/] [arithpack.vhd] - Rev 88

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Rev	Log message	Author	Age	Path
82	FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd	jguarin2002	4916d 10h	/raytrac/trunk/fpbranch/arithpack.vhd
81	Almost There	jguarin2002	4920d 08h	/arithpack.vhd
77	Now support for addition and substraction of A(7,10) component vectors	jguarin2002	4932d 20h	/arithpack.vhd
76	Upgrade para obtener una mantissa de 20 bits	jguarin2002	4934d 18h	/arithpack.vhd
74	On the rush, correct chip floor planning problem	jguarin2002	4941d 07h	/arithpack.vhd
73	Almost Ready Division and Square Root	jguarin2002	4942d 11h	/arithpack.vhd
60	Shifter circuit for Division Phase one done	jguarin2002	4952d 16h	/arithpack.vhd
59	Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt	jguarin2002	4955d 22h	/arithpack.vhd
52	Working......	jguarin2002	5002d 09h	/arithpack.vhd
50	There's now a descent testbench\!\!\!	jguarin2002	5010d 14h	/arithpack.vhd
49	Test bench ifs finally running	jguarin2002	5011d 09h	/arithpack.vhd
47	Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation	jguarin2002	5014d 17h	/arithpack.vhd
45	Magic is already written... now we shall set the testbench on fire\!	jguarin2002	5016d 08h	/arithpack.vhd
44	All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif...	jguarin2002	5017d 09h	/arithpack.vhd
43	Nothing to say, just working on the Test Bench...	jguarin2002	5017d 17h	/arithpack.vhd
42	no comment no tb yet:	jguarin2002	5018d 10h	/arithpack.vhd
40	test bench changes.....	jguarin2002	5020d 21h	/arithpack.vhd
32	carry_logic parameter added to uf entity	jguarin2002	5030d 23h	/arithpack.vhd
27	Optimized code, using IEEE libraries and extra parameters to make a more legible code	jguarin2002	5045d 06h	/arithpack.vhd
26	Corrections on opcoder	jguarin2002	5045d 10h	/arithpack.vhd

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[/] [raytrac/] [trunk/] [fpbranch/] [arithpack.vhd] - Rev 88

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