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[/] [reed_solomon_decoder/] [trunk/] [simulation/] [do.do] - Rev 2

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2 Initial commit of Reed Solomon Decoder Verilog core (204,188,8)
corrects up to 8 errors per block
Pipelined and verfied on FPGA
aelmahmoudy 5604d 04h /reed_solomon_decoder/trunk/simulation/do.do

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